Name
Title | ||
|---|---|---|
Inter-plane via defect detection using the sensor plane in 3D heterogeneous sensor systems |
Abstract | ||
|---|---|---|
Defect and fault tolerance is being studied in a 3D heterogeneous sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other planes which provide analog processing, digital signal processing, and wireless communication/networking. The sensor plane contains four types of transducers: visible imager (active pixel sensor), near IR and mid IR imager, and seismic and acoustic sensor arrays. This paper investigates ways of introducing defect and fault tolerance into the inter-plane via connections between the sensor and digital signal processing planes. The methodology detects failures in the inter-plane vias by inputting controlled signal patterns in each sensor type on the sensor plane. The sensor/via fault distribution in turn impacts the defect avoidance in the fault tolerant TESH network, which binds both the sensors and the processors that analyze and fuse the sensor plane data. Fault tolerance in the design and fabrication of the micromachined IR bolometers is also studied. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DFTVS.2005.42 | defect and fault tolerance in vlsi and nanotechnology systems |
Keywords | Field | DocType |
cmos image sensors,acoustic transducers,array signal processing,fault diagnosis,fault tolerance,infrared imaging,micromechanical devices,system-on-chip,3d heterogeneous sensor systems,acoustic sensor arrays,active pixel sensors,controlled signal patterns,defect avoidance,defect tolerance,fault detection,fault distribution,fault tolerant tesh network,inter-plane via defect detection,micromachined ir bolometers,mid ir imagers,near ir imagers,seismic sensor arrays,sensor planes,visible imagers,active pixel sensor,sensor array,chip,system on chip,digital signal processing,wireless communication,fault tolerant | Sensor node,Transducer,Digital signal processing,Computer science,Sensor array,CMOS sensor,Electronic engineering,Real-time computing,Chip,Fault tolerance,Analog signal processing | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-2464-8 | 4 |
PageRank | References | Authors |
0.72 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Glenn H. Chapman | 1 | 167 | 34.10 |
| Vijay Jain | 2 | 50 | 13.06 |
| S. Bhansali | 3 | 30 | 8.09 |