Paper Info
Title
Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention
Abstract
A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) [1-3] to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to insure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100 X) reducing the refresh power. Experimental results of a test system are presented.
Year
DOI
Venue
1999
10.1109/DFTVS.1999.802898
Albuquerque, NM
Keywords
Field
DocType
DRAM chips,Reed-Solomon codes,error correction codes,fault tolerance,DRAMs,adaptive refresh rate controller,data integrity,data pattern sensitivity,fault-tolerant refresh power reduction,memory system power usage,one-shot Reed-Solomon error correction code,part-to-part variations,perturbation effects,quasi-nonvolatile data retention
Dynamic random-access memory,Dram,Data retention,Computer science,Real-time computing,Error detection and correction,Refresh rate,Fault tolerance,Data integrity,Computer hardware,Memory refresh
Conference
ISSN
ISBN
Citations 
1550-5774
0-7695-0325-x
17
PageRank 
References 
Authors
1.99
4
4
Name
Order
Citations
PageRank
Yasunao Katayama18517.18
Eric J. Stuckey2171.99
Sumio Morioka349345.23
Zhao Wu4253.92