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SUMIO MORIOKA
Author Info
Open Visualization
Name
Affiliation
Papers
SUMIO MORIOKA
IBM Japan Ltd, Tokyo Res Lab, IBM Res, Kanagawa 2428502, Japan
12
Collaborators
Citations
PageRank
19
493
45.23
Referers
Referees
References
990
255
135
Search Limit
100
990
Publications (12 rows)
Collaborators (19 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme.
0
0.34
2017
CLOC: Authenticated Encryption for Short Input.
16
1.11
2014
$\textnormal{\textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms.
42
1.36
2012
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI
12
1.25
2002
An Optimized S-Box Circuit Architecture for Low Power AES Design
104
7.51
2002
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m)
13
1.55
2001
A Compact Rijndael Hardware Architecture with S-Box Optimization
268
24.82
2001
Efficient error correction code configurations for quasi-nonvolatile data retention by DRAMs
2
0.42
2000
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems
4
0.68
2000
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder
11
3.56
1999
Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention
17
1.99
1999
Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach
4
0.65
1994
1