Paper Info
Title
A state-serial Viterbi decoder architecture for digital radio on FPGA
Abstract
This paper proposes an area-efficient Viterbi decoder architecture for digital radio receivers, which exploits the new features offered by modern FPGA. Implementation results show that our architecture meets the throughput requirements for the DAB and DRM standards, while consuming extremely few hardware resources
Year
DOI
Venue
2005
10.1109/FPT.2005.1568582
Singapore
Keywords
Field
DocType
Viterbi decoding,digital radio,field programmable gate arrays,logic design,radio receivers,standards,DAB standards,DRM standards,digital radio receivers,field programmable gate arrays,state-serial Viterbi decoder architecture
Logic synthesis,Digital radio,Architecture,Computer science,Field-programmable gate array,Real-time computing,Exploit,Viterbi decoder,Radio receiver,Throughput
Conference
ISBN
Citations 
PageRank 
0-7803-9407-0
0
0.34
References 
Authors
2
2
Name
Order
Citations
PageRank
Mihail Petrov1375.69
Manfred Glesner21121255.04