| Embedded systems design for smart system integration | 3 | 0.84 | 2013 |
| Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach | 16 | 0.59 | 2013 |
| Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs | 2 | 0.38 | 2012 |
| Implementation and outcomes of FPGA-based system design in Mongolian education | 1 | 0.39 | 2012 |
| A programmable look-up table-based interpolator with nonuniform sampling scheme | 1 | 0.40 | 2012 |
| Hardware acceleration of combined cipher and forward error correction for low-power wireless applications | 0 | 0.34 | 2012 |
| On-chip efficient Round-Robin scheduler for high-speed interconnection | 0 | 0.34 | 2011 |
| Adaptive and deadlock-free tree-based multicast routing for networks-on-chip | 21 | 0.78 | 2010 |
| Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes | 6 | 0.77 | 2009 |
| Networks-on-chip based on dynamic wormhole packet identity mapping management | 9 | 0.54 | 2009 |
| Characterising embedded applications using a UML profile | 4 | 0.49 | 2009 |
| A flexible floating-point wavelet transform and wavelet packet processor | 0 | 0.34 | 2009 |
| On the design of reconfigurable multipliers for integer and Galois field multiplication | 5 | 0.58 | 2009 |
| Towards a unique FPGA-based identification circuit using process variations | 13 | 1.77 | 2009 |
| An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs | 0 | 0.34 | 2008 |
| High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor | 0 | 0.34 | 2008 |
| Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters | 0 | 0.34 | 2008 |
| PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels | 0 | 0.34 | 2008 |
| Comparison of opamp-based and comparator-based delta-sigma modulation | 3 | 0.74 | 2008 |
| Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects | 5 | 0.53 | 2008 |
| An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks | 7 | 0.58 | 2008 |
| Coarse-grained reconfiguration | 0 | 0.34 | 2008 |
| Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes | 2 | 0.38 | 2007 |
| On The Evolution Of Remote Laboratories For Prototyping Digital Electronic Systems | 18 | 1.74 | 2007 |
| Inserting Data Encoding Techniques into NoC-Based Systems | 11 | 0.62 | 2007 |
| System Level Design of a Dynamically Self-Reconfigurable Image Processing System | 1 | 0.37 | 2007 |
| A CMOS compatible charge recovery logic family for low supply voltages | 0 | 0.34 | 2006 |
| A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits | 0 | 0.34 | 2006 |
| Towards an Automated Design of Application-specific Reconfigurable Logic | 0 | 0.34 | 2006 |
| Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis | 2 | 0.37 | 2006 |
| Adaptive coding in networks-on-chip: transition activity reduction versus power overhead of the codec circuitry | 6 | 0.52 | 2006 |
| Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006 | 36 | 8.84 | 2006 |
| Multitasking Support for Dynamically Reconfig Urable Systems | 1 | 0.52 | 2006 |
| An Actor-Oriented Model-Based Design Flow for Systems-on-Chip | 1 | 0.37 | 2006 |
| Implementation of Realtime and Highspeed Phase Detector on FPGA | 4 | 0.78 | 2006 |
| Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten | 3 | 0.50 | 2005 |
| Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC | 0 | 0.34 | 2005 |
| Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator | 2 | 0.40 | 2005 |
| Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model | 0 | 0.34 | 2005 |
| HW/SW design and realization of a size-reconfigurable DCT accelerator | 1 | 0.40 | 2005 |
| Functional modeling techniques for a wireless LAN OFDM transceiver | 0 | 0.34 | 2005 |
| Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks | 1 | 0.36 | 2005 |
| Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata | 0 | 0.34 | 2005 |
| A state-serial Viterbi decoder architecture for digital radio on FPGA | 0 | 0.34 | 2005 |
| A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture | 0 | 0.34 | 2004 |
| Lookup-based Remote Laboratory for FPGA Digital Design Prototyping | 2 | 0.49 | 2004 |
| Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren | 1 | 0.36 | 2004 |
| IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter | 0 | 0.34 | 2004 |
| Design Of A Reconfigurable Aes Encryption/Decryption Engine For Mobile Terminals | 9 | 0.67 | 2004 |
| A low-IF architecture for dual-standard GSM/UMTS fully integrated receivers | 0 | 0.34 | 2003 |
