Paper Info
Title
Hierarchical test generation for systems on a chip
Abstract
The rapid increase in functionality on a single chip in the last few years has increased the gap between the complexity of the design and the capability of commercial test tools. In particular, the test needs for systems on a chip (SOC) are not addressed by existing tools. Because some of the cores integrated on a single SOC may not have embedded testability features, it is not always possible to use conventional design for testability (DFT) methodologies directly.This paper presents a novel approach for generating tests for complex SOCs which targets one module (or core) at a time, by extracting its environment elegantly in the form of constraints and storing it as virtual logic. Information about the core processor and internal bus is used to reduce the size of the virtual logic so that a commercial ATPG tool can be used to generate tests. These tests are then automatically translated to system-level tests. The approach is illustrated with an example SOC based on the picoJava core.
Year
DOI
Venue
2000
10.1109/ICVD.2000.812609
VLSI Design
Keywords
Field
DocType
Java,VLSI,application specific integrated circuits,automatic test pattern generation,design for testability,integrated circuit testing,ATPG tool,commercial test tools,constraints,core processor,design for testability,embedded testability features,functionality,hierarchical test generation,internal bus,picoJava core,system-level tests,systems on a chip,virtual logic
Design for testing,Testability,Automatic test pattern generation,System on a chip,Computer science,picoJava,Application-specific integrated circuit,Electronic engineering,Very-large-scale integration,Multi-core processor,Embedded system
Conference
ISSN
ISBN
Citations 
1063-9667
0-7695-0487-6
6
PageRank 
References 
Authors
0.72
6
3
Name
Order
Citations
PageRank
Raghuram S. Tupuri111410.63
J. Abraham24905608.16
Saab, D.G.318620.19