Title
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
Abstract
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology the lack of information on the physical implementation during logic synthesis has caused mismatches between the final circuit characteristics (delay, power and area) and those predicted by logic synthesis. In this paper, we present a technique that tightly links the logic and physical domains-we combine logic and placement optimization in a single step. The combined algorithm is based on simulation annealing and hence, very amenable to new optimization goals or constraints. Two types of moves, directed towards global reduction in the cost function (linear congestion), are accepted by the simulated annealing algorithm: (1) logic optimization steps consisting of removing or replacing redundant wires in a circuit using functional flexibilities derived from SPFDs and (2) the placement optimization steps consisting of swapping a pair of blocks in the FPGA. Feedback from placement is very valuable in making an informed choice of a target wire during logic optimization moves. Experimental results demonstrate the efficacy of our approach over the placement independent approach
Year
DOI
Venue
2000
10.1109/DATE.2000.840039
Paris
Keywords
Field
DocType
circuit optimisation,delays,field programmable gate arrays,integrated circuit layout,logic CAD,simulated annealing,FPGA design,cost function,delay reduction,linear congestion,power reduction,redundant wires,simulation annealing,simultaneous logic/placement optimization
Logic synthesis,Integrated circuit layout,Simulated annealing,Sequential logic,Logic optimization,Computer science,Field-programmable gate array,Real-time computing,Physical design,Register-transfer level
Conference
ISBN
Citations 
PageRank 
0-7695-0537-6
6
0.67
References 
Authors
8
2
Name
Order
Citations
PageRank
Balakrishna Kumthekar160.67
Fabio Somenzi23394302.47