Title
Deterministic logic BIST for transition fault testing
Abstract
Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault testing is not trivial as this necessitates the application of pattern pairs. As a consequence, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. With this in mind, the authors consider the so-called transition fault model, which is widely used for complexity reasons, and an extension of a DLBIST scheme for transition fault testing is presented. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated using difficult-to-test industrial designs
Year
DOI
Venue
2006
10.1109/ETS.2006.12
Computers & Digital Techniques, IET
Keywords
DocType
Volume
logic circuits,fault simulation,transition fault model,delay fault detection,transition fault testing,built-in self test,built-in self-test,logic overhead,fault diagnosis,stuck-at fault testing,deterministic logic BIST,deterministic logic bist,random pattern testability,delay test.,pattern testability,logic testing
Conference
1
Issue
ISSN
ISBN
3
1751-8601
0-7695-2566-0
Citations 
PageRank 
References 
7
0.53
21
Authors
4
Name
Order
Citations
PageRank
Valentin Gherman1363.35
Hans-Joachim Wunderlich21822155.30
Juergen Schloeffel3475.51
Michael Garbers470.53