Name
Abstract | ||
|---|---|---|
By using large threshold value in IDDQ tests, test time can be shortened. However, the fault coverage of the IDDQ tests will be affected by process variation. In this paper, effects on fault coverage of IDDQ tests generated by variations of zero biased threshold voltage of each MOS transistor in a circuit under test are examined with a circuit simulator. The result suggests us that IDDQ testing with large threshold value is applicable to production tests of CMOS ICs. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/DFTVS.2000.887177 | Yamanashi |
Keywords | Field | DocType |
CMOS logic circuits,integrated circuit testing,leakage currents,logic testing,production testing,CMOS ICs,IDDQ testing,MOS transistor,circuit simulator,fault coverage,large threshold value,process variation,production tests,test time reduction,testability analysis,zero biased threshold voltage variations | Fault coverage,Computer science,Threshold limit value,Real-time computing,CMOS,Electronic engineering,Iddq testing,Process variation,Transistor,Electronic circuit simulation,Threshold voltage | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-0719-0 | 0 |
PageRank | References | Authors |
0.34 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masaki Hashizume | 1 | 98 | 27.83 |
| Hiroyuki Yotsuyanagi | 2 | 70 | 19.04 |
| Takeomi Tamesada | 3 | 45 | 12.49 |
| Masashi Takeda | 4 | 0 | 0.34 |