Name
Abstract | ||
|---|---|---|
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. Prior to test, the test sets corresponding to cores under test (CUT) are merged by using the proposed merging algorithm to obtain a shared test set with minimum size. During test, the on-chip scan chain disable signal (SCDS) generator is employed to retrieve the original test vectors from the shared test set. The approach is non-intrusive and automatic test pattern generator (ATPG) independent. Moreover, the approach can reduce test cost further by combining with general test compression/decompression technique. Experimental results for ISCAS 89 benchmark circuits have proven the efficiency of the proposed approach. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/DATE.2006.243928 | Design, Automation and Test in Europe, 2006. DATE '06. Proceedings |
Keywords | Field | DocType |
automatic test equipment,automatic test pattern generation,system-on-chip,ATPG,CUT,SOC,automatic test equipment,automatic test pattern generator,concurrent core test,cores under test,multiple cores,scan chain disable signal,shared test set,test compression/decompression,test cost | Automatic test pattern generation,System on a chip,Computer science,Automatic test equipment,Parallel computing,Scan chain,Real-time computing,Merge (version control),Electronic circuit,Test compression,Test set | Conference |
Volume | ISSN | ISBN |
1 | 1530-1591 | 3-9810801-1-4 |
Citations | PageRank | References |
7 | 0.49 | 18 |
Authors | ||
2 | ||