Name
Abstract | ||
|---|---|---|
Static power dissipation due to transistor leakage constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations. Developing power efficient products will require consideration of static power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating static power consumption at the architectural level: Pstatic=VCC·N·k design·Iˆleak, where VCC is the supply voltage, N is the number of transistors, kdesign is a design dependent parameter, and Iˆleak is a technology dependent parameter. This model enables high-level reasoning about the likely static power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the high-level designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for static power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/MICRO.2000.898070 | Monterey, CA |
Keywords | DocType | ISSN |
computer architecture,integrated circuit design,integrated circuit modelling,leakage currents,low-power electronics,microprocessor chips,power consumption,power utilisation,alternative microarchitectures,architects,architectural level,design dependent parameter,design partitioning,design styles,high-level designs,high-level reasoning,less leaky transistors,microarchitecture definition,modern semiconductor technologies,performance penalty,power efficient products,process generations,scaling arguments,slower transistors,static power,static power consumption,static power demands,static power dissipation,static power model,static power optimization,supply voltage,technology dependent parameter,technology trends,total power dissipation,transistor leakage,unused devices,power optimization,power efficiency,power dissipation,low latency | Conference | 1072-4451 |
ISBN | Citations | PageRank |
0-7695-0924-X | 197 | 16.23 |
References | Authors | |
18 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Adam Butts | 1 | 249 | 19.76 |
| Gurindar S. Sohi | 2 | 2655 | 301.82 |