Name
Abstract | ||
|---|---|---|
We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/92.902268 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
delays,design for testability,flip-flops,logic testing,sequential circuits,combinational logic,design for testability,fault coverage,flip-flop,partial scan design,path delay testability,signal transition,synchronous sequential circuit | Design for testing,Testability,Sequential logic,Fault coverage,Computer science,Signal transition,Circuit design,Real-time computing,Combinational logic,Electronic engineering,Flip-flop | Journal |
Volume | Issue | ISSN |
8 | 6 | 1063-8210 |
Citations | PageRank | References |
5 | 0.48 | 17 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tapan J. Chakraborty | 1 | 258 | 26.11 |
| Vishwani D. Agrawal | 2 | 3502 | 470.06 |
| Michael L. Bushnell | 3 | 462 | 82.27 |