Paper Info
Title
Testable design of sequential circuits with improved fault efficiency
Abstract
A new synthesis and design-for-testability (DFT) technique is proposed for improving fault efficiency in non-scan synchronous sequential circuits. Certain simple constraints are imposed on state encoding prior to synthesis, and then a DFT technique is employed that guarantees absence of all sequentially undetectable faults, such as invalid, equivalent and isomorph. If the netlist is available instead of state description, only the DFT technique is applied, by skipping the synthesis part. The proposed design guarantees significantly lower test generation time, higher fault coverage, and almost complete fault efficiency, when sequential test generation tools are used. Experiments on MCNC and ISCAS 89 benchmark circuits show encouraging results. Hardware overhead of the proposed method compares favorably with that of full-scan.
Year
DOI
Venue
2001
10.1109/ICVD.2001.902651
VLSI Design
Keywords
Field
DocType
automatic test pattern generation,design for testability,fault diagnosis,integrated circuit testing,logic testing,sequential circuits,DFT technique,ISCAS 89 benchmark circuits,MCNC benchmark circuits,design-for-testability technique,equivalent faults,fault coverage,fault efficiency,hardware overhead,invalid faults,isomorph faults,netlist,nonscan synchronous sequential circuits,sequential circuits,sequential test generation tools,sequentially undetectable faults,simple constraints,state encoding,test generation time,testable design
Design for testing,Stuck-at fault,Netlist,Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Electronic engineering,Real-time computing,Benchmark (computing),Encoding (memory)
Conference
ISSN
ISBN
Citations 
1063-9667
0-7695-0831-6
1
PageRank 
References 
Authors
0.35
17
4
Name
Order
Citations
PageRank
Debesh K. Das113224.41
Bhargab B. Bhattacharya2848118.02
Satoshi Ohtake313521.62
Hideo Fujiwara418420.31