Name
Abstract | ||
|---|---|---|
Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction procedure considering the maximum current available in the serial transistor array. Validation of this modeling is obtained by comparing calculated gate output transition time to simulated ones (HSPICE level and foundry card model on 0.18µ m process). |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ISCAS.2001.922060 | Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium |
Keywords | Field | DocType |
CMOS logic circuits,delays,integrated circuit modelling,logic gates,CMOS gate performances,closed form expression,deep submicron CMOS structures,input ramp conditions,inverter maximum current,output fall times,output rise times,output transition time modeling,propagation delay,reduction procedure,serial transistor array,short circuit power dissipation | Delay calculation,Logic gate,Transistor array,Propagation delay,Pass transistor logic,Computer science,Closed-form expression,CMOS,Electronic engineering,Integrated injection logic,Electrical engineering | Conference |
Volume | ISBN | Citations |
5 | 0-7803-6685-9 | 8 |
PageRank | References | Authors |
0.95 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Maurine | 1 | 142 | 14.46 |
| Mustapha Rezzoug | 2 | 8 | 0.95 |
| Daniel Auvergne | 3 | 145 | 31.67 |