Name
Title | ||
|---|---|---|
2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing |
Abstract | ||
|---|---|---|
This paper describes the design of a fully integrated phase-locked loop for clock and data recovery applications. A two-stage ring oscillator modified for high-speed applications is proposed. The new proposed two-stage VCO features a self-skewing local action per stage. This leads to a significant improvement in speed up to 3 times than the conventional one. An operation up to 2GHz under 0.9mW power consumption with 1V supply is achieved using a standard 0.18 mum process. The chip active area is 0.1times0.1 mm2 |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693309 | Island of Kos |
Keywords | Field | DocType |
UHF oscillators,integrated circuit design,phase locked loops,synchronisation,voltage-controlled oscillators,0.18 micron,1 V,2 GHz,clock recovery,data recovery,phase locked loops,ring oscillator,self-skewing,voltage controlled oscillators,low power,low voltage,self-skewing,two-stage ring VCO | Phase-locked loop,Ring oscillator,Clock recovery,Computer science,Control theory,Chip,Electronic engineering,Voltage-controlled oscillator,Integrated circuit design,Jitter,RLC circuit | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 4 |
PageRank | References | Authors |
0.49 | 3 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amr Elshazly | 1 | 242 | 28.08 |
| K. Sharaf | 2 | 5 | 1.21 |