Name
Abstract | ||
|---|---|---|
A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISSCC.2006.1696078 | San Francisco, CA |
Keywords | DocType | ISSN |
cmos memory circuits,high-speed integrated circuits,random-access storage,0.13 micron,200 mbit/s,60 ns,64 mbit,bl-bl coupling noise,cmos technology,feram,burst mode,cell data write back scheme,high speed ecc circuit,quad-bl architecture,read-write cycle time,cycle time | Conference | 0193-6530 |
ISBN | Citations | PageRank |
1-4244-0079-1 | 9 | 1.70 |
References | Authors | |
1 | 15 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Katsuhiko Hoya | 1 | 32 | 5.33 |
| Daisaburo Takashima | 2 | 78 | 26.66 |
| Shinichiro Shiratake | 3 | 46 | 8.34 |
| Ryu Ogiwara | 4 | 32 | 5.33 |
| Tadashi Miyakawa | 5 | 37 | 6.52 |
| Hidehiro Shiga | 6 | 41 | 15.51 |
| Sumiko Doumae | 7 | 32 | 5.67 |
| shinichi ohtsuki | 8 | 9 | 2.03 |
| Yoshinori Kumura | 9 | 32 | 4.99 |
| S. Shuto | 10 | 35 | 8.21 |
| T Ozaki | 11 | 314 | 38.13 |
| K. Yamakawa | 12 | 37 | 8.35 |
| Iwao Kunishima | 13 | 32 | 5.33 |
| Akihiro Nitayama | 14 | 32 | 4.99 |
| seizo fujii | 15 | 9 | 1.70 |