Name
Abstract | ||
|---|---|---|
A 66GHz maximum operating clock frequency is measured for a 90nm CMOS static CML divide-by-2 with a 25.5mW latch power dissipation. Statistical self-oscillation frequency measurements exhibit a mean of 42.6 and 39.2GHz at 25degC and 85degC, and a 2.8GHz standard deviation. The mean dissipated power is 44.3mW at 1.4V, with a 2.2mW standard deviation |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISSCC.2006.1696274 | San Francisco, CA |
Keywords | DocType | ISSN |
cmos logic circuits,clocks,current-mode logic,frequency dividers,millimetre wave frequency convertors,1.4 v,2.2 mw,2.8 ghz,25 c,25.5 mw,39.2 ghz,42.6 ghz,44.3 mw,66 ghz,85 c,90 nm,cmos integrated circuits,current mode logic,latch power dissipation,static cml divider,statistical self-oscillation,power dissipation,oscillations,standard deviation | Conference | 0193-6530 |
ISBN | Citations | PageRank |
1-4244-0079-1 | 6 | 1.31 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Plouchart, J.-O. | 1 | 31 | 5.54 |
| jonghae kim | 2 | 6 | 1.31 |
| v karam | 3 | 6 | 1.31 |
| robert trzcinski | 4 | 6 | 1.31 |
| julian d gross | 5 | 6 | 1.31 |