Paper Info
Title
Simultaneous switching noise and resonance analysis of on-chip power distribution network
Abstract
This paper presents a frequency-domain technique for finding the worst-case time-domain voltage variations in the RLC power bus of digital VLSI circuits. Pattern independent maximum envelope currents are used for the logic gates and macroblocks. The voltage drop/surge at a power bus node is expressed in term of the currents using sensitivity analysis. The sensitivity information together with an optimization procedure are applied to find the upper-bounds on the voltage variations at the targeted bus nodes. The resonance problem due to the on-chip RLC power distribution network is analyzed base on the frequency-domain sensitivity analysis. Comparisons to SPICE simulation of circuits extracted from layouts are used to validate our approach.
Year
DOI
Venue
2002
10.1109/ISQED.2002.996723
ISQED
Keywords
Field
DocType
SPICE,VLSI,circuit optimisation,circuit resonance,circuit simulation,digital integrated circuits,electric potential,frequency-domain analysis,integrated circuit layout,integrated circuit modelling,integrated circuit noise,power supply circuits,sensitivity analysis,RLC power bus,SPICE simulation,circuit layouts,digital VLSI circuits,frequency-domain sensitivity analysis,frequency-domain technique,logic gates,macroblocks,on-chip RLC power distribution network,on-chip power distribution network,optimization procedure,pattern independent maximum envelope currents,power bus node,resonance analysis,sensitivity analysis,simultaneous switching noise,voltage drop,voltage surge,worst-case time-domain voltage variations
Logic gate,Spice,Computer science,Voltage,Voltage drop,Electronic engineering,Electronic circuit,Electrical engineering,RLC circuit,Very-large-scale integration,Busbar
Conference
ISBN
Citations 
PageRank 
0-7695-1561-4
6
0.57
References 
Authors
6
2
Name
Order
Citations
PageRank
Geng Bai160.57
Ibrahim N. Hajj257279.52