Name
Abstract | ||
|---|---|---|
This paper describes a wide-range clock generation phase-locked loop (PLL) incorporating several features that make it suitable for integration in highly scaled processes. A fully dif- ferential supply regulated tuning scheme is used to combat power supply noise. The charge pump uses a resistor rather than an active current source to define the pumping current in order to reduce the charge pump flicker noise. Fabricated in a 0.18- m CMOS process, the PLL occupies 0.15 mm die area and achieves a fre- quency range of 0.5 to 2.5 GHz. When operating at 2.4 GHz, the power consumption is 14 mA from a 1.8-V supply while the jitter is 2.36 ps rms. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.884194 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
CMOS integrated circuits,UHF integrated circuits,circuit tuning,flicker noise,integrated circuit noise,phase locked loops,power supply circuits,voltage multipliers,voltage-controlled oscillators,0.18 micron,0.5 to 2.5 GHz,1.8 V,14 mA,2.36 ps,CMOS process,charge pump,flicker noise,fully differential supply regulated tuning,power supply noise,pumping current,voltage-controlled oscillator,wide-range clock generation phase-locked loop,Phase-locked loop,charge pump,flicker noise,power supply noise,supply regulation,voltage-controlled oscillator | Journal | 41 |
Issue | ISSN | Citations |
12 | 0018-9200 | 20 |
PageRank | References | Authors |
2.87 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Merrick Brownlee | 1 | 20 | 2.87 |
| Pavan Kumar Hanumolu | 2 | 240 | 27.03 |
| Kartikeya Mayaram | 3 | 20 | 2.87 |
| Un-Ku Moon | 4 | 115 | 28.82 |