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PAVAN KUMAR HANUMOLU
Author Info
Open Visualization
Name
Affiliation
Papers
PAVAN KUMAR HANUMOLU
Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
16
Collaborators
Citations
PageRank
35
240
27.03
Referers
Referees
References
677
180
68
Search Limit
100
677
Publications (16 rows)
Collaborators (35 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C
1
0.43
2021
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques
16
1.08
2014
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops
25
1.95
2013
Analog Filter Design Using Ring Oscillator Integrators
16
1.05
2012
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators
0
0.34
2012
A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity
2
0.36
2012
Continuous-Time Input Pipeline ADCs
3
0.51
2010
A Digital PLL With a Stochastic Time-to-Digital Converter
37
5.90
2009
A 1V downconversion filter using duty-cycle controlled bandwidth tuning
0
0.34
2008
A Wide-Tracking Range Clock and Data Recovery Circuit
39
3.15
2008
Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters
12
1.60
2007
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance
3
0.53
2007
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
46
4.60
2007
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning
13
1.24
2006
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning
20
2.87
2006
A 1.6Gbps Digital Clock and Data Recovery Circuit
7
1.08
2006
1