Paper Info
Title
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
Abstract
As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter. Therefore, it becomes important to route the nets within tight minimum and maximum length bounds. Although the problem of routing nets to satisfy maximum length constraints is a well-studied problem, there exists no sophisticated algorithm in literature that ensures that minimum length constraints are also satisfied. In this paper, the authors propose a novel algorithm that effectively incorporates the min;max length constraints into the routing problem. The approach is to use a Lagrangian-relaxation (LR) framework to allocate extra routing resources around nets simultaneously during routing them. The authors also propose a graph model that ensures that all the allocated routing resources can be used effectively for extending lengths. Their routing algorithm automatically prioritizes resource allocation for shorter nets and length minimization for longer nets so that all nets can satisfy their min;max length constraints. This paper demonstrates that this algorithm is effective even in the cases where length constraints are tight, and the spacing between adjacent nets is small
Year
DOI
Venue
2006
10.1109/TCAD.2006.882584
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions
Keywords
DocType
Volume
VLSI,graph theory,minimax techniques,network routing,printed circuit design,Lagrangian-relaxation,VLSI,graph model,high-performance printed circuit boards,length-matching routing algorithm,min-max length constraints,routing nets,very large scale integration,Algorithms,Lagrangian relaxation,printed circuit board (PCB),routing,very large scale integration (VLSI)
Journal
25
Issue
ISSN
Citations 
12
0278-0070
37
PageRank 
References 
Authors
2.46
14
2
Name
Order
Citations
PageRank
Muhammet Mustafa Ozdal131323.18
Martin D. F. Wong2604.16