Paper Info
Title
The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture
Abstract
A multi-threaded, dynamically trace-based architecture is presented, designed to make fuller usage of the PEs of a VLIW. The mDTSVLIW extends our single process DTSVLIW design to reduce the effect of both horizontal and vertical waste, and of variable latencies. The DTSVLIW performs single instruction execution of a process, dynamically scheduling these in hardware into blocks of VLIW instructions for VLIW execution. The mDTSVLIW maintains these features and adds simultaneous multithreading by issuing and executing instructions from VLIW blocks from several threads. Preliminary experiments to explore the design varied the number of threads, scalar processors and cache sizes. Results achieve PE utilization of up to 87% on a 4-thread, 1- scalar, 8 PE design, with speed-ups of up to 6.3 that of a single processor. Noticeably it only needs a single scalar process to be scheduled at any time, with main memory fetches being 1-4% that of a single processor.
Year
DOI
Venue
2006
10.1109/SBAC-PAD.2006.28
Ouro Preto
Keywords
DocType
ISSN
multi-threading,parallel architectures,scheduling,dynamic scheduling,multithreaded trace-based vliw architecture,simultaneous multithreading,single instruction process execution,vliw,computer architecture
Conference
1550-6533
ISBN
Citations 
PageRank 
0-7695-2704-3
1
0.36
References 
Authors
5
2
Name
Order
Citations
PageRank
P. Rounce1122.19
De Souza, A.F.210.70