Name
Abstract | ||
|---|---|---|
Rewiring has been used extensively for optimizing the area, the power consumption, the delay, and the testabil- ity of a circuit. In this work, we demonstrate how rewiring can also be used for reducing the Soft Error Rate (SER). We employ an ATPG-based rewiring method to generate functionally-equivalent yet structurally-different implemen- tations of a logic circuit based on simple transformation rules. This rewiring capability, along with an off-the-shelf method for assessing the SER of a circuit, enable the integra- tion of the SER in a unified search algorithm that iteratively evolves the design in order to satisfy a given set of objec- tives. Experimental results on ISCAS'89 and ITC'99 bench- mark circuits verify that rewiring can indeed be successfully used to reduce the SER of a circuit and, thus, it facilitates a design-space exploration framework for trading off area, power consumption, delay, testability, and SER. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TEST.2006.297682 | Santa Clara, CA |
Keywords | Field | DocType |
automatic test pattern generation,integrated circuit design,integrated circuit testing,integrated logic circuits,logic design,logic testing,ATPG-based rewiring,ISCAS'89,ITC'99,circuit area optimization,circuit delay,circuit testability,logic circuit,power consumption,rewiring-based design space exploration,soft error rate | Logic synthesis,Testability,Automatic test pattern generation,Logic gate,Search algorithm,Soft error,Computer science,Real-time computing,Electronic engineering,Integrated circuit design,Design space exploration | Conference |
ISSN | ISBN | Citations |
1089-3539 E-ISBN : 1-4244-0292-1 | 1-4244-0292-1 | 23 |
PageRank | References | Authors |
1.22 | 21 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sobeeh Almukhaizim | 1 | 166 | 15.48 |
| Yiorgos Makris | 2 | 1365 | 107.21 |
| Yu-Shen Yang | 3 | 92 | 8.23 |
| A. Veneris | 4 | 937 | 67.52 |