Name
Abstract | ||
|---|---|---|
With the increase in issue width, bypass control of a processor become more complex. Also, in a processor, operands are read both from register file as well as from bypass. For a multi-port register file, read/write energy is much more than that of single port register file. Both redundant register read/write and bypass control area can be reduced with compiler hints for register bypass. In this work we suggest a innovative way to represent compiler bypass hints that serve both these motivations. Further, bypass hints are used in effective design of multi-stage bypass network. Experiments on mediabench benchmarks show that by using our approach, (i) register file energy savings can be as as much as 60% (ii) and synthesis of VLIW core saves 2-4% of the core area. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSID.2007.127 | VLSI Design |
Keywords | Field | DocType |
instruction sets,logic design,microprocessor chips,program compilers,VLIW processor,bypass control area,compiler driven bypass network,multiport register file,power reduction,redundant register read/write,register bypass | Status register,Register allocation,Computer science,Memory data register,Parallel computing,Register file,Stack register,Control register,Real-time computing,Register window,Processor register,Operating system | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2762-0 | 12 |
PageRank | References | Authors |
0.71 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Neeraj Goel | 1 | 12 | 0.71 |
| Anshul Kumar | 2 | 399 | 48.45 |
| Preeti Ranjan Panda | 3 | 786 | 89.40 |