Name
Abstract | ||
|---|---|---|
This paper proposes an analytical method to assess soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. SER and execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each failure mode in the SoC are used to compute the System- Failure Rate (SFR) of the SoC. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VTS.2007.9 | Berkeley, CA |
Keywords | Field | DocType |
Unified Modeling Language,failure analysis,integrated circuit design,integrated circuit modelling,system-on-chip,SoC designs,UML based system level failure rate assessment,UML model,soft-error rate,software cores,system-on-chip | Failure mode and effects analysis,Opcode,System on a chip,Unified Modeling Language,Computer science,Executable UML,Failure rate,Real-time computing,Electronic engineering,Integrated circuit design,Software,Reliability engineering | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2812-0 | 3 |
PageRank | References | Authors |
0.70 | 11 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad Hosseinabady | 1 | 146 | 15.21 |
| M. H. Neishaburi | 2 | 79 | 7.51 |
| Lotfi-Kamran, P. | 3 | 396 | 22.26 |
| Zainalabedin Navabi | 4 | 303 | 51.08 |