Name
Abstract | ||
|---|---|---|
In this paper, we present optimized methodology for Intra-task voltage scheduling. Our proposed method gets data flow and control flow of application that represents coloration between different parts of the application at the early stage of design using UML-RT model and decides to schedule processor's voltage. By applying this technique on JPEG encoder system experimental results show reduction in energy consumption by 18-54 % over common Intra-DVS algorithm. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/AICCSA.2007.370928 | AICCSA |
Keywords | Field | DocType |
Unified Modeling Language,data flow computing,power aware computing,processor scheduling,IntraDVS algorithms,UML-RT model,control flow,data flow,intra-task voltage scheduling,processor scheduling,system level voltage scheduling technique | Dynamic voltage scaling,Unified Modeling Language,Scheduling (computing),Computer science,Voltage,Control flow,Transform coding,Real-time computing,Energy consumption,Data flow diagram | Conference |
ISSN | ISBN | Citations |
2161-5322 | 1-4244-1031-2 | 0 |
PageRank | References | Authors |
0.34 | 9 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. H. Neishaburi | 1 | 79 | 7.51 |
| Masoud Daneshtalab | 2 | 0 | 0.34 |
| Majid Nabi | 3 | 0 | 0.34 |
| Siamak Mohammadi | 4 | 62 | 10.62 |