Name
Title | ||
|---|---|---|
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform |
Abstract | ||
|---|---|---|
The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. JPEG2000 standard defines an irreversible DWT by a lifting scheme of factorized coefficients using (9, 7) Daubechies coefficients. The paper proposed optimizations on lifting based 1D-DWT data flow graph resulting in a new pipelining scheme, which is more power-efficient than existing approaches. The authors have shown that the constant multipliers defined by JPEG2000 standard, have latency of about 1.6 times the general adder latency. Hence, while finding the critical path, the basic assumption of multiplier latency being much greater than the adder latency does not hold for DWT in JPEG2000. How 75% multiplications can be reduced at the scaling step by this 2D-DWT implementation was also shown. This multiplication reduction not only saves power but also results in area saving by eliminating three multipliers in the hardware |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.378484 | New Orleans, LA |
Keywords | Field | DocType |
coprocessors,discrete wavelet transforms,image coding,pipeline processing,JPEG2000 image compression,area saving,lifting-based 2D-discrete wavelet transform,multiplier latency,pipelined VLSI architecture,power saving | Pipeline (computing),Lifting scheme,Adder,Computer science,Transform coding,Second-generation wavelet transform,Electronic engineering,Discrete wavelet transform,JPEG 2000,Wavelet transform | Conference |
ISSN | ISBN | Citations |
0271-4302 | 1-4244-0921-7 | 5 |
PageRank | References | Authors |
0.52 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rahul Jain | 1 | 5 | 0.52 |
| Preeti Ranjan Panda | 2 | 786 | 89.40 |