Name
Abstract | ||
|---|---|---|
The current generations of FPGA comprise of many specialized hardware cores, like embedded processors, multipliers, RAMs and FIFOs, along with the regular arrays of reconfigurable logic. On any FPGA device, these embedded cores are located at fixed locations only. This makes the task of floorplanning for the applications with heterogeneous components very difficult. Recently, some researchers have started looking into this problem of heterogeneous floorplanning on FPGA. However, all these work suffer from one fundamental flaw which affects the quality of solutions leading to higher device areas or excessively high runtime. In this paper, we propose a heterogeneous floorplanner for the FPGA, HPlan, which is fast and highly efficient in finding floorplans of variety of resources. We present a case study of a real implementation on Xilinx Virtex device. The proposed floorplanner could effectively implement the design with tight resource constraints whereas the traditional floorplanner could not find a feasible floorplan. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/FCCM.2007.31 | VLSI Design |
Keywords | Field | DocType |
circuit layout,field programmable gate arrays,logic design,reconfigurable architectures,FPGA device,Xilinx Virtex device,embedded processor,hardware core,heterogeneous floorplanner,reconfigurable logic array,resource constraint | Logic synthesis,Computer architecture,Computer science,Programmable logic array,Parallel computing,Field-programmable gate array,Real-time computing,Virtex,Floorplan,Reconfigurable computing,Programmable logic device,Embedded system | Conference |
ISBN | Citations | PageRank |
978-0-7695-2940-0 | 1 | 0.36 |
References | Authors | |
13 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Love Singhal | 1 | 61 | 6.22 |
| Elaheh Bozorgzadeh | 2 | 630 | 37.93 |