Name
Abstract | ||
|---|---|---|
With increasing embedded application complexity, designers have proposed to introduce new hardware architectures based on heterogeneous processing units on a single chip. For these architectures, the scheduling service of a realtime operating system must be able to assign tasks on different execution resources. This paper presents a model of artificial neural networks used for real-time task scheduling to heterogeneous system-on-chip architectures. Our proposition is an adaptation of the Hopfield model and the main objective concerns the minimization of the neuron number to facilitate future hardware implementation of this service. In fact, to ensure rapid convergence and low complexity, this number must be dramatically reduced. So, we propose new constructing rules to design smaller neural network and we show, through simulations, that network stabilization is obtained without reinitialisation of the network. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/IJCNN.2007.4370938 | Orlando, FL |
Keywords | Field | DocType |
Hopfield neural nets,real-time systems,scheduling,system-on-chip,Hopfield model,artificial neural networks,hardware architectures,heterogeneous SoC architectures,realtime operating system,realtime task scheduling,system-on-chip | Scheduling (computing),Computer science,Embedded applications,Minification,Artificial intelligence,Artificial neural network,Distributed computing,System on a chip,Chip,Real-time operating system,Rapid convergence,Machine learning,Embedded system | Conference |
ISSN | ISBN | Citations |
1098-7576 E-ISBN : 978-1-4244-1380-5 | 978-1-4244-1380-5 | 2 |
PageRank | References | Authors |
0.38 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Chillet | 1 | 193 | 26.12 |
| Pillement, Sebastien | 2 | 33 | 5.30 |
| Olivier Sentieys | 3 | 597 | 73.35 |