| A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency | 0 | 0.34 | 2021 |
| Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-on-Chip Architecture | 0 | 0.34 | 2020 |
| Energy-Efficient Scheduling of Real-Time Tasks in Reconfigurable Homogeneous Multicore Platforms | 1 | 0.35 | 2020 |
| Run-Time management of energy-performance trade-off in Optical Network-on-Chip. | 0 | 0.34 | 2018 |
| Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects. | 0 | 0.34 | 2018 |
| Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. | 0 | 0.34 | 2017 |
| Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC. | 1 | 0.36 | 2017 |
| Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms | 0 | 0.34 | 2016 |
| Power Modeling And Exploration Of Dynamic And Partially Reconfigurable Systems | 0 | 0.34 | 2016 |
| New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems. | 0 | 0.34 | 2015 |
| Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip | 3 | 0.39 | 2015 |
| Communication Aware Design Method for Optical Network-on-Chip | 1 | 0.36 | 2015 |
| Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA | 2 | 0.40 | 2014 |
| Intrinsic Fault Tolerance of Hopfield Artificial Neural Network Model for Task Scheduling Technique in SoC. | 0 | 0.34 | 2014 |
| Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC | 0 | 0.34 | 2014 |
| Special issue on design and architectures of real-time image processing in embedded systems | 4 | 0.40 | 2014 |
| Power consumption models for the use of dynamic and partial reconfiguration. | 2 | 0.37 | 2014 |
| Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource | 1 | 0.39 | 2013 |
| An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. | 12 | 0.66 | 2013 |
| UPaRC: ultra-fast power-aware reconfiguration controller | 8 | 0.63 | 2012 |
| Power consumption model for partial and dynamic reconfiguration. | 12 | 0.65 | 2012 |
| Open-People: Open Power and Energy Optimization PLatform and Estimator | 6 | 0.67 | 2012 |
| Towards a power and energy efficient use of partial dynamic reconfiguration | 1 | 0.35 | 2011 |
| Parallel Evaluation of Hopfield Neural Networks. | 0 | 0.34 | 2011 |
| Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network | 3 | 0.40 | 2011 |
| AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. | 3 | 0.47 | 2011 |
| Hardware OS Communication Service and Dynamic Memory Management for RSoCs | 3 | 0.37 | 2011 |
| Parallelism Level Impact on Energy Consumption in Reconfigurable Devices | 4 | 0.53 | 2011 |
| Open-people: open power and energy optimization PLatform and estimator | 0 | 0.34 | 2010 |
| Mesh and Fat-Tree comparison for dynamically reconfigurable applications. | 0 | 0.34 | 2010 |
| Task placement for dynamic and partial reconfigurable architecture | 5 | 0.48 | 2010 |
| Flexible interconnection network for dynamically and partially reconfigurable architectures | 6 | 0.63 | 2010 |
| R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip | 2 | 0.39 | 2010 |
| High-Level Exploration for Dynamic Reconfiguration Management | 0 | 0.34 | 2009 |
| OveRSoC: a framework for the exploration of RTOS for RSoC platforms | 6 | 0.60 | 2009 |
| Structure mémoire reconfigurable. Vers une structure de stockage faible consommation | 0 | 0.34 | 2008 |
| A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources | 4 | 0.51 | 2008 |
| Hardware task scheduling for heterogeneous soc architectures | 0 | 0.34 | 2007 |
| A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures | 2 | 0.38 | 2007 |
| Floating-to-fixed-point conversion for digital signal processors | 39 | 1.80 | 2006 |
| Exploring RTOS issues with a high-level model of a reconfigurable SoC platform | 3 | 0.42 | 2005 |
| Co-Design of Massively Parallel Embedded Processor Architectures | 9 | 0.67 | 2005 |
| Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe | 0 | 0.34 | 2003 |
| A Compilation Framework for a Dynamically Reconfigurable Architecture | 2 | 0.39 | 2002 |
| Automatic floating-point to fixed-point conversion for DSP code generation | 25 | 1.65 | 2002 |
| Behavioral IP specification and integration framework for high-level design reuse | 2 | 0.80 | 2002 |
| DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints | 6 | 0.55 | 2002 |
| A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals | 2 | 0.46 | 2001 |
| Multi-algorithm ASIP synthesis and power estimation for DSP applications | 6 | 0.69 | 2000 |
| A Framework for High Level Estimations of Signal Processing VLSI Implementations | 4 | 0.45 | 2000 |
