Name
Abstract | ||
|---|---|---|
A new design for a mismatch-tolerant on-chip data jitter measurement circuit in 0.11-mum CMOS is experimentally verified in this paper. It utilizes a data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The circuit's tolerance to data-rate changes is verified using 2.5 Gbps and 2.98 Gbps PRBS signals. The jitter gain of the prototype circuit is also shown to be less sensitive to variations in the supply voltage. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405704 | San Jose, CA |
Keywords | Field | DocType |
CMOS integrated circuits,convertors,integrated circuit testing,jitter,CMOS,complementary metal-oxide-semiconductor,data-to-clock converter,integrator,jitter gain,mismatch-tolerant circuit,on-chip data jitter measurement circuit,pulse generator,size 0.11 mum | Computer science,Voltage,Integrator,CMOS,Electronic engineering,Pulse generator,Mixed-signal integrated circuit,Jitter,Diode-or circuit,Asynchronous circuit | Conference |
ISBN | Citations | PageRank |
978-1-4244-1623-3 | 0 | 0.34 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiyotaka Ichiyama | 1 | 19 | 4.95 |
| Masahiro Ishida | 2 | 105 | 22.58 |
| Takahiro J. Yamaguchi | 3 | 176 | 35.24 |
| Mani Soma | 4 | 497 | 73.41 |