Name
Abstract | ||
|---|---|---|
With the density of field-programmable gate arrays (FPGAs) steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpose nature has limited the use of FPGAs in scientific applications that require floating-point arithmetic due to the large amount of FPGA resources that floating-point operations still require. This paper considers three architectural modifications that make floating-point operations more efficient on FPGAs. The first modification embeds floating-point multiply-add units in an island-style FPGA. While offering a dramatic reduction in area and improvement in clock rate, these embedded units are a significant change and may not be justified by the market. The next two modifications target a major component of IEEE compliant floating-point computations: variable length shifters. The first alternative to lookup tables (LUTs) for implementing the variable length shifters is a coarse-grained approach: embedded variable length shifters in the FPGA fabric. These shifters offer a significant reduction in area with a modest increase in clock rate and are smaller and more general than embedded floating-point units. The next alternative is a fine-grained approach: adding a 4:1 multiplexer unit inside a configurable logic block (CLB), in parallel to each 4-LUT. While this offers the smallest overall area improvement, it does offer a significant improvement in clock rate with only a trivial increase in the size of the CLB. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TVLSI.2007.912041 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
field programmable gate arrays,floating point arithmetic,table lookup,IEEE compliant floating-point computation,architectural modification,clock rate,configurable logic block,field-programmable gate array,floating-point arithmetic,floating-point multiply-add units,floating-point performance,lookup table,reconfigurable architecture,variable length shifter,Field-programmable gate array (FPGA),floating-point arithmetic,reconfigurable architecture | Lookup table,Computer science,Floating point,Field-programmable gate array,Electronic engineering,Multiplexer,Logic block,Multiplexing,Computer hardware,Clock rate,Embedded system,Computation | Journal |
Volume | Issue | ISSN |
16 | 2 | 1063-8210 |
Citations | PageRank | References |
20 | 1.06 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael J. Beauchamp | 1 | 77 | 5.53 |
| Scott Hauck | 2 | 2539 | 232.71 |
| Keith D. Underwood | 3 | 847 | 77.39 |
| K. Scott Hemmert | 4 | 577 | 50.62 |