Paper Info
Title
A Programmable Load/Store Unit on C-based Hardware Design for FPGA
Abstract
This paper proposes to introduce a programmable load/store unit (LSU) to C-based hardware design for an FPGA. The LSU provides flexible memory access methods that can hide memory access latency for hardware modules generated by a high-level synthesis tool. The hardware module with the LSU can treat efficiently not only simple streaming accesses but also sophisticated accesses such as image processing. The LSU is evaluated using two case studies. The result shows that the LSU can significantly reduce the burden of designing the dedicated memory access circuits and the hardware modules with the LSU achieve a speedup of 16.5 and 27.3 times compared with an embedded processor.
Year
DOI
Venue
2007
10.1109/FPT.2007.4439286
Kitakyushu
Keywords
Field
DocType
C language,field programmable gate arrays,image processing,integrated circuit design,system-on-chip,C-based hardware design,FPGA,SOC,flexible memory access methods,hardware modules,high-level synthesis tool,image processing,memory access circuits,memory access latency,programmable load-store unit,system-on-chips
System on a chip,Access method,Computer science,Programmable load,Latency (engineering),Parallel computing,Image processing,Field-programmable gate array,Integrated circuit design,Computer hardware,Embedded system,Speedup
Conference
ISBN
Citations 
PageRank 
978-1-4244-1472-7
0
0.34
References 
Authors
4
2
Name
Order
Citations
PageRank
Akira Yamawaki1179.36
Masahiko Iwane2133.79