Paper Info
Title
A 10 000 fps CMOS Sensor With Massively Parallel Image Processing
Abstract
A high speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 m standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 m 35 m pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four- quadrant multiplier architecture. The retina provides address- event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values. A 64 64 pixel proof-of-concept chip was fabricated. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2 000 to 5 000 frames per second.
Year
DOI
Venue
2008
10.1109/JSSC.2007.916618
Solid-State Circuits, IEEE Journal of  
Keywords
Field
DocType
cmos integrated circuits,pixel,fpga,imaging,cmos image sensor,image processing,computer architecture,concurrent computing,cmos technology,convolutional codes,chip,very large scale integration,convolution,proof of concept,cmos sensor,photodiode,field programmable gate arrays,photodiodes,vlsi,frames per second
Vision chip,Image sensor,Massively parallel,Computer science,Image processing,CMOS sensor,Sobel operator,Electronic engineering,Frame rate,Pixel,Computer hardware
Journal
Volume
Issue
ISSN
43
3
0018-9200
Citations 
PageRank 
References 
36
2.39
16
Authors
4
Name
Order
Citations
PageRank
Julien Dubois114618.76
D. Ginhac2373.46
Michel Paindavoine311521.70
B. Heyrman4495.88