Title
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput
Abstract
Within-die parameter variations can cause wide delay distribution among similar functional units in superscalar processors. Conventionally, the frequency of operation is reduced to accommodate the slowest unit, which in turn degrades throughput. We present a low-overhead design technique that sets the operating frequency in a superscalar processor based on the faster units and allows more cycles for the slower units. We propose an associated priority scheduling strategy to schedule instructions in the functional units to maximize throughput. Simulation results on a set of benchmarks show that, by assigning a higher scheduling priority to faster units, we can achieve 18 percent improvement in performance on average with negligible design overhead.
Year
DOI
Venue
2008
10.1109/TC.2008.40
Computers, IEEE Transactions
Keywords
Field
DocType
instruction sets,microprocessor chips,processor scheduling,delay distribution,instruction scheduling,low-overhead design,operation frequency,priority scheduling,superscalar processors,within-die variation-aware scheduling,Scheduling,Superscalar Processors,Variable-cycle functional unit,process variation,speed binning.
Operating frequency,Instruction scheduling,Computer science,Scheduling (computing),Instruction set,Parallel computing,Real-time computing,Process variation,Throughput,Priority scheduling,Superscalar
Journal
Volume
Issue
ISSN
57
7
0018-9340
Citations 
PageRank 
References 
11
0.75
15
Authors
4
Name
Order
Citations
PageRank
Patrick Ndai111012.00
Swarup Bhunia21952168.49
Amit Agarwal369372.95
Kaushik Roy41531142.83