Name
Abstract | ||
|---|---|---|
In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been called parasitic-aware synthesis. This solution, as such, is not yet complete since there are geometric requirements (minimization of area or fulfillment of certain layout aspect ratio, among others) whose effects on the resulting parasitics are not usually considered during the electrical synthesis. In this paper, a layout-aware solution for analog cells that tackles both geometric and parasitic-aware electrical synthesis is proposed. Several design examples are provided. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCAD.2008.923417 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
analogue integrated circuits,integrated circuit design,integrated circuit layout,network synthesis,analog cells,analog integrated circuit design,electrical syntheses,integrated layout synthesis,parasitic aware synthesis,physical syntheses,Analog integrated circuit (IC),design automation,floorplan sizing,layout parasitics,layout-aware synthesis | Journal | 27 |
Issue | ISSN | Citations |
7 | 0278-0070 | 39 |
PageRank | References | Authors |
1.71 | 20 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Castro-Lopez, R. | 1 | 41 | 2.09 |
| Guerra, O. | 2 | 39 | 1.71 |
| Elisenda Roca | 3 | 129 | 26.84 |
| Fernandez, F.V. | 4 | 39 | 1.71 |