Name
Abstract | ||
|---|---|---|
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globally asynchronous, locally synchronous (GALS) design approaches should take over. The design of circuits using complex field programmable components like state of the art FPGAs follows this same trend. In GALS design, a critical step is the definition of asynchronous interfaces between synchronous regions. This paper proposes SCAFFI, a new asynchronous interface to interconnect modules inside FPGAs. The interface is based on clock stretching techniques to avoid metastability. Differently from other interfaces, it can use both logic levels for stretching and do not require the use of arbiters. Also, compactness of the implementation is enhanced by the use of dedicated FPGA hard macros. A GALS version implementation of an RSA cryptography core demonstrates the use of SCAFFI. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICCD.2007.4601950 | Lake Tahoe, CA |
Keywords | Field | DocType |
VLSI,cryptography,field programmable gate arrays,network synthesis,FPGAs,GALS,RSA cryptography core,SCAFFI,VLSI design,clock stretching techniques,field programmable gate arrays,globally asynchronous, locally synchronous design,hard macros,intrachip FPGA asynchronous interface,synchronous VLSI circuits | Asynchronous communication,Synchronization,Asynchronous system,Computer science,Cryptography,Field-programmable gate array,Real-time computing,Electronic circuit,Macro,Very-large-scale integration,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-6404 E-ISBN : 978-1-4244-1258-7 | 978-1-4244-1258-7 | 16 |
PageRank | References | Authors |
0.90 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pontes, J. | 1 | 16 | 0.90 |
| Soares, R. | 2 | 17 | 1.26 |
| Carvalho, E. | 3 | 16 | 0.90 |
| Fernando Moraes | 4 | 720 | 43.62 |