Name
Abstract | ||
|---|---|---|
In this paper a reconfigurable size MDCT accelerator is modeled and synthesized. Starting from the C code of the desired application that cannot run in real time on the given platform (a LEON processor) we isolate the computationally extensive modules of the MDCT to be implemented an accelerator. Because of similarities of their data flow graphs we modify the R2SDF architecture of the FFT and fit it to the MDCT algorithm by adding modules to solve the irregularities in its data flow graphs. The resultant architecture is modular and size-reconfigurable. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ICECS.2005.4633437 | Gammarth |
Keywords | Field | DocType |
data flow graphs,digital signal processing chips,discrete cosine transforms,fast Fourier transforms,hardware-software codesign,logic design,FFT,HW/SW design,MDCT algorithm,R2SDF architecture,data flow graph,digital signal processing system,discrete cosine tranform accelerator,hardware-software design,size-reconfigurable DCT accelerator | Logic synthesis,Graph,Computer science,Parallel computing,Discrete cosine transform,Data-flow analysis,Fast Fourier transform,Modular design,Discrete cosine transforms,Data flow diagram | Conference |
ISBN | Citations | PageRank |
978-9972-61-100-1 | 1 | 0.40 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdulfattah Mohammad Obeid | 1 | 1 | 0.40 |
| Tudor Murgan | 2 | 1 | 0.40 |
| Abdelouahid Taadou | 3 | 1 | 0.40 |
| Manfred Glesner | 4 | 1121 | 255.04 |