Name
Abstract | ||
|---|---|---|
This paper describes a downconversion filter which uses variable delay clocks to simultaneously perform downconversion mixing and filter bandwidth tuning. This method of bandwidth tuning is highly linear and applicable to low supply voltages. The test chip fabricated in a 0.18 mum CMOS process achieves 19.2 dBV IIP3 at 1 V and has a bandwidth that is tunable over a -50% range. The downconversion filter mixes and filters an 830 MHz input to a nominal 300 kHz bandwidth at DC. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/CICC.2008.4672185 | San Jose, CA |
Keywords | Field | DocType |
CMOS integrated circuits,low-pass filters,mixers (circuits),CMOS process,downconversion filter,duty-cycle controlled bandwidth tuning,frequency 830 MHz,variable delay clocks,voltage 1 V | Duty cycle,Computer science,Voltage,Control engineering,Electronic engineering,Cmos process,CMOS,Chip,Bandwidth (signal processing),Low-pass filter,Filter bandwidth | Conference |
ISBN | Citations | PageRank |
978-1-4244-2019-3 | 0 | 0.34 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter Kurahashi | 1 | 0 | 0.34 |
| Pavan Kumar Hanumolu | 2 | 240 | 27.03 |
| Un-Ku Moon | 3 | 36 | 5.04 |