Name
Abstract | ||
|---|---|---|
A wideband millimeter-wave (mmWave) CML static divider fabricated in 65 nm SOI CMOS technology is presented. The mmWave system realization trend and engagement in sub-100 nm CMOS technologies are summarized. CML static dividerpsilas circuit analysis, sensitivity curve, and simulations are explored. The input-locking hysteresis and divider DC bias tuning are employed to extend the divider operation range. The divider performance measurements are presented with hysteresis-assisted gain and figure-of-merits. A scalable statistical estimation is proposed, and it is validated with a full 300 mm wafer measurements. The divider exhibits wideband mmWave performance to overcome the process variability in sub-100 nm CMOS processes. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/CICC.2008.4672164 | San Jose, CA |
Keywords | Field | DocType |
CMOS integrated circuits,circuit tuning,millimetre wave circuits,sensitivity analysis,silicon-on-insulator,statistical analysis,SOI CMOS technology,circuit analysis,divider DC bias tuning,input-locking hysteresis,sensitivity curve,size 65 nm,statistical estimation,wafer measurements,wideband CML static divider,wideband millimeter-wave CML static divider fabrication | Silicon on insulator,Wideband,Wafer,Computer science,Electronic engineering,CMOS,DC bias,Network analysis,Electrical engineering,Soi cmos technology,Scalability | Conference |
ISBN | Citations | PageRank |
978-1-4244-2019-3 | 2 | 0.42 |
References | Authors | |
21 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daeik D. Kim | 1 | 2 | 0.42 |
| Choongyeun Cho | 2 | 40 | 6.76 |
| Jonghae Kim | 3 | 2 | 0.42 |
| Plouchart, J.-O. | 4 | 31 | 5.54 |