Name
Abstract | ||
|---|---|---|
Multiprocessors Systems-on-Chip (MPSoCs) are a trend in VLSI design, since they minimize the design crisis represented by the gap between the silicon technology and the actual SoC design capacity. MPSoCs may employ NoCs to in- tegrate several programmable processors, specialized memo- ries, and other specific IPs in a scalable way. Besides commu- nication infrastructure, another important issue in MPSoCs is task mapping. Dynamic task mapping is needed, since the number of tasks running in the MPSoC may exceed the avail- able resources. Most works in literature present static mapping solutions, not appropriate for this scenario. This paper investi- gates the performance of mapping algorithms in NoC-based heterogeneous MPSoCs, targeting NoC congestion minimiza- tion. The use of the proposed congestion-aware heuristics re- duces the NoC channel load, congestion, and packet latency. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISSOC.2008.4694878 | Tampere |
Keywords | DocType | ISBN |
VLSI,logic design,network-on-chip,NoC,VLSI design,congestion-aware task mapping,dynamic task mapping,heterogeneous MPSoC,multiprocessors systems-on-chip | Conference | 978-1-4244-2542-6 |
Citations | PageRank | References |
41 | 1.36 | 17 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ewerson Carvalho | 1 | 41 | 1.36 |
| Fernando Moraes | 2 | 720 | 43.62 |