Name
Abstract | ||
|---|---|---|
Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700686 | Santa Clara, CA |
Keywords | Field | DocType |
integrated circuit yield,redundancy,system-on-chip,SoC yield,TMR,triple modular redundancy | System on a chip,Computer science,Triple modular redundancy,Electronic engineering,Real-time computing,Redundancy (engineering),Dual modular redundancy,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-3539 E-ISBN : 978-1-4244-2403-0 | 978-1-4244-2403-0 | 2 |
PageRank | References | Authors |
0.52 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Vial | 1 | 26 | 3.06 |
| A. Bosio | 2 | 113 | 15.51 |
| P. Girard | 3 | 478 | 41.91 |
| Landrault, C. | 4 | 185 | 41.42 |