Name
Title | ||
|---|---|---|
A 0.7 V Single-Supply SRAM With 0.495 m Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme |
Abstract | ||
|---|---|---|
We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/JSSC.2009.2014009 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
CMOS digital integrated circuits,SRAM chips,amplifiers,integrated circuit design,low-power electronics,nanoelectronics,CMOS technology,SRAM,cascaded bit line scheme,high-density cell,low-supply-voltage,memory size 256 KByte,self-write-back sense amplifier,single-supply operation,size 65 nm,voltage 0.6 V,voltage 0.7 V,Low-power design,SRAM,divided bit line,ultra-high-density cell | Journal | 44 |
Issue | ISSN | Citations |
4 | 0018-9200 | 20 |
PageRank | References | Authors |
1.56 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keiichi Kushida | 1 | 61 | 4.86 |
| Suzuki, A. | 2 | 35 | 4.56 |
| Fukano, G. | 3 | 20 | 1.56 |
| Kawasumi, A. | 4 | 20 | 1.56 |