7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme | 6 | 0.46 | 2016 |
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture | 16 | 1.10 | 2015 |
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction | 3 | 0.47 | 2012 |
A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers | 12 | 0.82 | 2011 |
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers | 4 | 0.45 | 2010 |
A 0.7 V Single-Supply SRAM With 0.495 m Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme | 20 | 1.56 | 2009 |