Name
Abstract | ||
|---|---|---|
Asynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity. However,asynchronous design styles are largely incompatible with clocked CAD,which has prevented wide-scale adoption. The key incompatibility istiming. Thus most commercial work relies on custom CAD or untimeddelay-insensitive design methodologies. This paper proposes a newmethodology, based on formal verification and relative timing, tocreate and prove correct necessary constraints to support asynchronousdesign with traditional clocked CAD. These constraints support timingdriving synthesis, place and route, and behavior and timing validationof fully asynchronous designs using traditional clocked CAD flows.This flow is demonstrated through a simple example pipeline in IBM's 65 nm process showing the ability to retarget the design for improved power and performance. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ASYNC.2009.26 | Chapel Hill, NC |
Keywords | Field | DocType |
asynchronous circuits,circuit CAD,clocks,timing circuits,asynchronous circuit design,asynchronous templates,clocked CAD flows | CAD,Asynchronous communication,Logic gate,Pipeline transport,IBM,Computer architecture,Computer science,Place and route,Electronic design automation,Formal verification | Conference |
ISSN | ISBN | Citations |
1522-8681 | 978-1-4244-3933-1 | 22 |
PageRank | References | Authors |
1.15 | 17 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kenneth S. Stevens | 1 | 185 | 25.65 |
| Yang Xu | 2 | 22 | 1.15 |
| Vikas S. Vij | 3 | 31 | 2.52 |