Name
Title | ||
|---|---|---|
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration |
Abstract | ||
|---|---|---|
This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39-14] ps effective resolution consuming [1-8] mA, in an area of only 0.26 mm2. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ESSCIRC.2011.6044960 | ESSCIRC |
Keywords | Field | DocType |
calibration,convertors,phase detectors,all-digital time-to-digital converter,gain tracking,on-line background calibration,reconfigurable resolution,spatial oversampling,standard cell,sub-gate delay | Oversampling,Computer science,Chip,Electronic engineering,Design flow,Standard cell,Time-to-digital converter,Calibration | Conference |
ISSN | ISBN | Citations |
1930-8833 E-ISBN : 978-1-4577-0702-5 | 978-1-4577-0702-5 | 4 |
PageRank | References | Authors |
0.51 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kameswaran Vengattaramane | 1 | 4 | 0.51 |
| Jonathan Borremans | 2 | 221 | 30.47 |
| Michiel Steyaert | 3 | 599 | 165.88 |
| Craninckx, J. | 4 | 4 | 0.51 |