Name
Title | ||
|---|---|---|
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10−19 |
Abstract | ||
|---|---|---|
We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operation. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 384 sets of unique 128-bit fingerprints from 12 chips, which were evaluated in this paper. The fail rate of the ID was found to be 4.45 × 10-19 at a nominal supply voltage of 1.2 V and at room temperature. This scheme can be implemented for existing SRAMs through minor modifications. It has high speed, and is implemented in a very small area overhead. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ESSCIRC.2011.6044938 | ESSCIRC |
Keywords | Field | DocType |
SRAM chips,fingerprint identification,128-bit chip identification generating scheme,SRAM bitcells,transistor characteristics,unique fingerprint,voltage 1.2 V | Computer science,Failure rate,Static random-access memory,Chip,128-bit,Embedded system | Conference |
Volume | Issue | ISSN |
112 | 15 | 1930-8833 E-ISBN : 978-1-4577-0702-5 |
ISBN | Citations | PageRank |
978-1-4577-0702-5 | 5 | 0.50 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shunsuke Okumura | 1 | 63 | 12.54 |
| Shusuke Yoshimoto | 2 | 30 | 12.56 |
| Hiroshi Kawaguchi | 3 | 395 | 91.51 |
| Masahiko Yoshimoto | 4 | 6 | 2.22 |