Paper Info
Title
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
Abstract
Regular multi-core processors are appearing in the embedded system market as high performance software pro- grammable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at different levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility of representative k-ary n-mesh topologies and by providing silicon-aware system-level performance figures. properties in terms of diameter, average minimal hop count and bisection bandwidth. In contrast, topologies with more than 2 dimensions are attractive for a number of reasons. First, increasing the number of dimensions in a mesh results in higher bandwidth and reduced latency. Second, the number of dimensions can be traded-off with the number of cores per switch, thus giving rise to concentrated topologies saving network components and trading bandwidth for latency. Third, wiring on a chip comes at a lower cost with respect to off-chip interconnections. However, wiring is also the challenging aspect of these topolo- gies, since their mapping on a bidimensional plane involves the existence of wires with different lengths. Depending on the physical design technique, the more complex connectivity pattern may impact performance, area and power in different ways, such as a decreased operating frequency or a higher link latency. The objective of this paper is to assess performance of k- ary n-mesh topologies while considering design constraints posed by real-life HW/SW MPSoC platforms. This makes the analysis more insightful and trustworthy than traditional abstract exploration frameworks based on pencil-and-paper floorplanning considerations. These latter often ignore the presence of non-routable hard IP blocks, the asymmetric tile size, the use of link pipelining to sustain network speed or the dependence of switch critical path on its radix. The relentless scaling of silicon technology to the nanoscale regime is making the interconnect delay issue even more critical and is causing the network critical path to move from the logic to global network links. By leveraging a backend synthesis flow for regular NoC architectures, we characterize the mapping efficiency of a given topology on the silicon layout, targeting a 65nm technology node. We extract physical parameters from the physical synthesis and expose them to the system-level simulation tool, thus coming up with silicon-aware performance figures. At this level, network performance is usually characterized by means of synthetic traffic patterns (such as uniform or hot-spot), in the best case reflecting average communication bandwidth of real- life applications. This paper aims to go a step further, by con- sidering the requirements that a recently proposed middleware library for MPSoC communication poses on the underlying interconnect fabric. In essence, we consider network traffic generated by synchronization mechanisms implemented in software. Finally, we provide a model of the chip I/O interface, thus capturing the implications of I/O performance on that of specific k-ary n-mesh topologies.
Year
DOI
Venue
2009
10.1109/CISIS.2009.30
Fukuoka
Keywords
Field
DocType
circuit CAD,integrated circuit interconnections,microprocessor chips,network topology,network-on-chip,MPSoC domain,embedded system,high performance software programmable solutions,interconnect fabric,interconnect reverse scaling,k-ary n-mesh topologies,multicore processors,network-on-chip topologies,off-chip interconnection networks,silicon-aware system-level performance,software constraints,synchronization mechanism,Networks-on-Chips,interconnection networks,topologies
Computer architecture,Synchronization,Computer science,Network on a chip,Network topology,Software,MPSoC,Multi-core processor,Distributed computing,Network interface,Scalability
Conference
ISBN
Citations 
PageRank 
978-0-7695-3575-3
9
0.57
References 
Authors
15
4
Name
Order
Citations
PageRank
Francisco Gilabert11337.02
Ludovici, D.2341.40
Medardoni, S.3933.53
Davide Bertozzi4165399.83