Enabling power efficiency through dynamic rerouting on-chip | 0 | 0.34 | 2013 |
Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoC | 1 | 0.40 | 2010 |
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology | 2 | 0.42 | 2010 |
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints | 9 | 0.57 | 2009 |
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints | 24 | 1.08 | 2009 |
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework | 20 | 1.21 | 2008 |
Deterministic versus Adaptive Routing in Fat-Trees | 77 | 3.00 | 2007 |