Name
Abstract | ||
|---|---|---|
Existing techniques for path delay fault (PDF) diagnosis prune fault-free candidates using nonfailing patterns but fail to reduce the size of suspect set significantly. This paper presents two alternative techniques that can be applied in a postprocessing manner to further reduce the suspect set by prioritizing paths using only the failing patterns. Experimental results on the ISCAS benchmarks demonstrate that they are time and memory efficient. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TVLSI.2009.2013469 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
failure analysis,fault diagnosis,integrated circuit testing,ISCAS benchmarks,nonfailing patterns,path delay fault diagnosis prune fault-free candidates,postprocessing,suspect set size reduction,Failure analysis,fault diagnosis,path delay faults (PDFs),testing | Cause effect analysis,Computer science,Pattern analysis,Path delay,Electronic engineering,Real-time computing,Suspect,Benchmark (computing) | Journal |
Volume | Issue | ISSN |
18 | 4 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 14 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajsekhar Adapa | 1 | 35 | 3.92 |
| Spyros Tragoudas | 2 | 625 | 88.87 |